Paging Confusion

[oib111]

On PTEs and PDEs the bits reserved for the frame address are only 20-bits. So you can really only represent addresses up to 1MB. So is the frame address really multiplied by 4K to get the physical address? So like if the frame address is 1 it represents the page at 4096-8191?

[Mike]

Hello,

It is not stressed to much in the paging chapter (although I suppose it should. It will be updated.) The frame address portion only stores the most significant 20 bits of the frame address, not the entire frame address. The entire frame address is the 32 bit PTE or PDE itself. However, because pages must be 4KB aligned, the least significant 12 bits will always be 0. The architecture uses this fact and takes advantage of it by adding flags to the unused bits.

Thus, the frame address is not the entire frame address - only the top 20 bits of it. The rest of the 32 bit address is 0. Thus the smallest you can use is 0, second is 4096, and largest is, of course, 4gb. You cannot use any address that is not a multiple of 4k do to this.

[oib111]

Thanks that cleared that up!